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Title:
CLOCK DATA RECOVERY CIRCUITRY ASSOCIATED WITH PROGRAMMABLE LOGIC DEVICE CIRCUITRY
Document Type and Number:
Japanese Patent JP2010172014
Kind Code:
A
Abstract:

To provide clock data recovery circuitry provided on or associated with programmable logic device circuitry.

A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system.


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Inventors:
AUNG EDWARD
LUI HENRY
BUTLER PAUL
TURNER JOHN
PATEL RAKESH
LEE CHONG
Application Number:
JP2010101545A
Publication Date:
August 05, 2010
Filing Date:
April 26, 2010
Export Citation:
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Assignee:
ALTERA CORP
International Classes:
H04L7/033; H04L7/04; G11C7/22; H03K19/177; H03L7/07; H03L7/08; H03L7/081; H03L7/099; H03L7/187; H03M9/00; H04L7/02; H03L7/089; H03L7/199
Domestic Patent References:
JPH0758731A1995-03-03
JPH06327072A1994-11-25
JPH11317731A1999-11-16
JPH11317730A1999-11-16
JPS63108238U1988-07-12
JPH0648243U1994-06-28
JPH04199912A1992-07-21
JPH10134523A1998-05-22
JPH04274542A1992-09-30
JPH09149017A1997-06-06
JPS63121344A1988-05-25
JPH0758731A1995-03-03
JPH06327072A1994-11-25
JPH11317731A1999-11-16
JPH11317730A1999-11-16
JPS63108238U1988-07-12
JPH0648243U1994-06-28
JPH04199912A1992-07-21
Foreign References:
US6031428A2000-02-29
Other References:
JPN5003013961; Ｊａｓｏｎ　Ｋｏｎｓｔａｓ: 'Ｃｏｎｖｅｒｔｉｎｇ　Ｗｉｄｅ，　Ｐａｒｅｌｌｅｌ　Ｄａｔａ　ｂｕｓｅｓ　ｔｏ　Ｈｉｇｈ　Ｓｐｅｅｄ　Ｓｅｒｉａｌ　ｌｉｎｋｓ' Ｉｎｔｅｒｎａｔｉｏｎａｌ　ＩＣ　'９９　Ｃｏｎｆｅｒｅｎｃｅ　Ｐｒｏｃｅｅｄｉｎｇｓ , 1999, ｐ．１９-３０
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita



 
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