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Patent Searching and Data


Title:
CLOCK DISCRIMINATING CIRCUIT
Document Type and Number:
Japanese Patent JPH04323709
Kind Code:
A
Abstract:

PURPOSE: To make a large scale integrated circuit of a circuit by taking in one clock selected from two clocks and outputting its clock information as the alarm of a logical value signal and discriminating the clock by the logical value.

CONSTITUTION: This circuit consists of a counter part 1 which takes in one clock selected from two clocks different in frequency, an alarm generating part 2 which outputs selected clock information as the alarm of the logical value signal, and an alarm discriminating part 3 which discriminates the clock by the logical value of this alarm. A selected clock A or B is taken as the load signal of the counter part 1. The counter part 1 counts the 'H' state of this taken-in selected clock and decodes the counted value to a value preliminarily set to a decoder 1a, and the decoded result is latched in the alarm generating part 2 and is outputted as the alarm. Consequently, the selected clock is discriminated in the alarm discriminating part 3.


Inventors:
TSUNEMATSU TOSHINOBU
Application Number:
JP9400091A
Publication Date:
November 12, 1992
Filing Date:
April 24, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F1/06; (IPC1-7): G06F1/06
Attorney, Agent or Firm:
Sadaichi Igita