Title:
クロック分周回路、及びクロック分周方法
Document Type and Number:
Japanese Patent JP5338819
Kind Code:
B2
Abstract:
A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit 20 and a mask circuit 10. The mask control circuit 20 includes a mask timing signal generation circuit 22 that generates a mask timing signal 29 used to preferentially mask a clock pulse at a timing other than communication timings among M clock pulses of the input clock signal based on a communication timing signal 26, and a mask restraint circuit 62 that carries out a process to restrain masking of a clock pulse at a communication timing. The mask circuit 10 generates an output clock signal by masking clock pulses of an input clock signal according to a mask signal 50 generated by the mask control circuit.
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| JPS55124331 | BIT RATE SIGNAL GENERATING CIRCUIT |
Inventors:
Mitsufumi Shibayama
Application Number:
JP2010542831A
Publication Date:
November 13, 2013
Filing Date:
December 02, 2009
Export Citation:
Assignee:
NEC
International Classes:
H03K23/64; H03K21/00
Domestic Patent References:
| JPS6382015A | 1988-04-12 | |||
| JPS637016A | 1988-01-12 | |||
| JPH0946222A | 1997-02-14 | |||
| JPS63151217A | 1988-06-23 |
Attorney, Agent or Firm:
Ken Ieiri