Title:
クロック分周回路、クロック分配回路、クロック分周方法及びクロック分配方法
Document Type and Number:
Japanese Patent JP5488470
Kind Code:
B2
Abstract:
A clock frequency divider circuit 11 according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by masking (S-N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency divider circuit 11 includes a mask control circuit that generates a mask signal in which a non-mask timing is preferentially assigned to a clock pulse at a timing at which no clock pulse exists in a clock signal used in a circuit Ai other than a target circuit Bi using the output clock signal among S clock pulses of the input clock signal, and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.
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Inventors:
Mitsufumi Shibayama
Application Number:
JP2010535622A
Publication Date:
May 14, 2014
Filing Date:
July 30, 2009
Export Citation:
Assignee:
NEC
International Classes:
H03K23/64; H03K5/15
Domestic Patent References:
| JPH0946222A | 1997-02-14 | |||
| JPS63151217A | 1988-06-23 | |||
| JPH05160721A | 1993-06-25 | |||
| JP2000035832A | 2000-02-02 | |||
| JP2001320022A | 2001-11-16 | |||
| JPH0946222A | 1997-02-14 | |||
| JPH05160721A | 1993-06-25 | |||
| JPH08125644A | 1996-05-17 | |||
| JPS63151217A | 1988-06-23 | |||
| JP2003330568A | 2003-11-21 | |||
| JP2000035832A | 2000-02-02 | |||
| JP2001320022A | 2001-11-16 |
Attorney, Agent or Firm:
Ken Ieiri