Title:
クロック分周回路、クロック分配回路、クロック分周方法及びクロック分配方法
Document Type and Number:
Japanese Patent JP5522050
Kind Code:
B2
Abstract:
To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S-N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.
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Inventors:
Mitsufumi Shibayama
Application Number:
JP2010535621A
Publication Date:
June 18, 2014
Filing Date:
July 30, 2009
Export Citation:
Assignee:
NEC
International Classes:
H03K23/64; G06F1/06; H03K5/15
Domestic Patent References:
| JP2000035832A | 2000-02-02 | |||
| JP2001320022A | 2001-11-16 | |||
| JPH0946222A | 1997-02-14 | |||
| JPH05160721A | 1993-06-25 | |||
| JPS63151217A | 1988-06-23 |
Attorney, Agent or Firm:
Ken Ieiri