Title:
クロック分周器とそのトリガ信号発生回路
Document Type and Number:
Japanese Patent JP4111932
Kind Code:
B2
Abstract:
A clock frequency divider is provided which has first to Pth (where P is an integer) sub-counters (SC1 to SCP), each capable of counting M+1 clock pulses and provided in parallel, and first to Pth clock signals (IC1 to ICP) are provided to the sub-counters, which have the same period as a reference clock signal (RCLK) and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first to Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.
Inventors:
Marutani Masazumi
Application Number:
JP2004152161A
Publication Date:
July 02, 2008
Filing Date:
May 21, 2004
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K21/00; H03K23/64; H03K23/44
Domestic Patent References:
| JP7050576A | ||||
| JP57018128A | ||||
| JP53076731A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku
Previous Patent: 電気伝導性複合酸化物結晶化合物及びその製造方法。
Next Patent: METHOD AND DEVICE FOR POSITIONING AND MOUNTING DIE OF PRESS MACHINE
Next Patent: METHOD AND DEVICE FOR POSITIONING AND MOUNTING DIE OF PRESS MACHINE