To provide a device capable of suppressing a clock frequency to low because a circuit operates at the frequency of an input clock, and reducing the power consumption of the circuit and heat generation associated therewith.

The circuit for generating a dividing clock is provided with a counter operating at an input clock, a selector for selecting a load signal of the counter, a holding circuit for holding an output bit of the counter at a clock having a phase reverse to the input clock, and a logic gate for generating a dividing clock from the output bit of the counter and an output signal of the holding circuit.