To adequately execute the re-timing processing of input data by judging the phase of an input signanl based on a specified secondary clock and adjusting a phase based on the third clock selected from the second clock.

A multi-phase clock generating circuit 20 generates plural clocks CLK1-CLK8 based on a frequency dividing clock CLK 1 from a PLL circuit 10 and a data edge detecting circuit 30 detects the rising/falling timing edges of input data so as to generate a pulse (e) at every timing cycle. An optimum phase judging circuit 40 counts the number of reference clocks betwewen the pulses (e) and outputs setting informamtion of a required position in input data and an optimum phase selecting circuit 50 selects an optimum phase clock from the clocks CLK1-CLK8 based on the information. A data re-timing circuit 70 adjusts the phase of delay data outputted from a timing adjusting circuit 60 based on the optimum phase clock and outputs an extraction clock CLK9 and extraction data.