PURPOSE: To secure the steady extraction of the clock by using the shift register to use the multiplied carrier extracted as the shift clock to the delay circuit in case the phase detection is given to the phase-modulated reception wave and then the clock is extracted by the demodulated signal.

CONSTITUTION: The modulated wave supplied to input terminal 501 is branched off into two parts, and one of the branched wave is supplied to phase detector 506 through resonator 503, slicer 504 and 1/2 divider 505 each along with another wave. Thus the modulated signal is decoded, and the output is branched off into two parts. One of the branched output is converted into the clock pulse by slicer 508 via clock extraction circuit 507 and then supplied to decision circuit 509 along with the other output. And the base band signal is delivered. One of demodulated signal (a) supplied to input 601 of clock component extraction circuit 507 is delayed by shift register 602 which gives shift lock to double-multiplied carrier (b) and then supplied to exclusive logic sum circuit 603 along with another demodulated signal to extract the clock component to output 604.