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Title:
CLOCK FAULT DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH03262319
Kind Code:
A
Abstract:

PURPOSE: To detect a clock fault even when a clock frequency is fluctuated increasingly or decreasingly by using two oscillators and counters with a different frequency to detect the fault in a short time such as clock momentary interruption.

CONSTITUTION: The relation such as fL<fIN<fH is satisfied among a clock frequency fIN being a fault detection object, a frequency fL of an oscillator OSC 1 and a frequency fH of an oscillator OSC 2. When the clock frequency fIN being a fault detection object is abnormal and fluctuated in a lower frequency and the relation of fIN<fL<fH is satisfied, since the operation speed of a counter CNT0 is reduced, the case of generation of two carrying signals (CO) of a counter CNT1 is present without fail for one period of a carry signal (CO) of the counter CNT0. Thus, the time when the counted value of a counter CNT 3 is 2 is present thereon and a signal appears at the output of a gate GT. Thus, the frequency abnormality is detected.


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Inventors:
OKASHITA KAZUHIRO
Application Number:
JP6293890A
Publication Date:
November 22, 1991
Filing Date:
March 13, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K5/19; (IPC1-7): H03K5/19
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)