To output a clock signal which has a prescribed duty and is synchronized with an input signal by forming the clock signal having the desired duty, based on the output signal of a latching means latching an input signal with a reference clock signal and a signal which is frequency-divided by a frequency dividing circuit.

A data input signal Td is taken into a flip-flop F/F-5 and the reset of a frequency dividing circuit is accordingly released. Thus, the flip-flops F/F-1 to F/F-4 start frequency dividing operations and a signal V6 obtained by frequency-dividing the reference clock KC by 1/5 is obtained from F/F-1. An output signal RBC of the flip-flop F/F-8 is synchronized with the rise of an output signal V5 and turns into a high level and turns into a low level in synchronizing with the next rise. Thus, F/F-8 outputs a signal obtained by frequency-dividing the output signal V5 of F/F-2 by two, namely, a signal obtained by frequency-dividing the reference clock KC by ten.