To reduce power consumption by reducing an operation voltage in a clock frequency divider circuit.

The clock frequency divider circuit includes: a counter for counting an input clock signal to form a D-ary count value; a counter for counting an output clock signal to form an N-ary count value, a toggle position-analyzing section for obtaining rise and fall toggle-enable signals from the output clock signal, the minimum cycle of the output clock, the semi-cycle accuracy difference of the output clock, the D-ary count value and the N-ary count value; a first flip-flop for toggling in accordance with the rise toggle-enable signal in a rise edge of the input clock signal; a second flip-flop for toggling in accordance with the fall toggle-enable signal in a fall edge of the input clock signal; and an exclusive-OR circuit for obtaining exclusive-OR between outputs via the first and second flip-flops and executing output clock.