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Patent Searching and Data


Title:
CLOCK FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JP2010258761
Kind Code:
A
Abstract:

To obtain an output clock signal by frequency-dividing an input clock signal in a frequency dividing ratio, that is represented with optional rational numbers, by enabling an output clock signal to rise in falling of the input clock signal.

An clock frequency divider circuit includes at least a computing unit 11, a computing unit 12a, and a comparator 108. An input clock signal 109 is frequency-divided in a frequency dividing ratio that is a value obtained by dividing a numerator setting value 112 by a denominator setting value 111. The computing unit 11 records the value of the input signal in synchronization with the input clock signal 109. Then, a generated computing unit output value 120 is output in response to the input clock signal 109. The computing unit 12a outputs the computing unit output value 120. The comparator 108 compares the computing unit output value 120 with the numerator setting value 112, and outputs a high signal or a low signal as an output clock signal 121. The computing unit output value 120 is fed back and input to the computing unit 11.


Inventors:
Usui, Masahiro
Application Number:
JP2009000106173
Publication Date:
November 11, 2010
Filing Date:
April 24, 2009
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H03K23/66; G06F1/06; G06F1/08; H03K21/00; H03K23/64; H03K23/68
Domestic Patent References:
JP2006165931A
JP2006148807A
JPH11340818A
Attorney, Agent or Firm:
家入 健