PURPOSE: To realize a frequency divider circuit having large frequency dividing ratio by a small-scale circuit by combining and decoding the outputs of plural ring counters having frequency dividing ratios in prime relation to each other.

CONSTITUTION: A clock signal CLOCK to be frequency-divided is inputted to four pieces of the ring counters 1 to 4, and these ring counters 1 to 4 connect continuously plural FFs respectively, and simultaneously, they feed back the output of each FF to the FF of a first stage through a NAND gate, and the frequency dividing ratio is determined by the number of pieces of the FFs. The frequency dividing numbers of the ring counters 1 to 4 are 4, 5, 7, 9 respectively, and they are in the relation prime to each other, namely, in the relation that one side is not the integral multiple of other side. The outputs of the ring counters 1 to 4 are inputted to the AND gate 5 of a decoding means, and the output of the AND gate 5 is outputted as the frequency divided output through the FFs 6,7. Thus, a circuit scale can be made small, and in addition, an influence to another circuit can be reduced.