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Title:
CLOCK FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD IN DELAY LOCKED LOOP
Document Type and Number:
Japanese Patent JP2004048729
Kind Code:
A
Abstract:

To provide a clock frequency divider and a clock frequency dividing method in a delay locked loop in which a frequency of an inputted external clock is automatically divided into a low frequency band or a high frequency band and an optimal divided frequency waveform is selected in accordance with the band.

The clock frequency divider in a DLL circuit for generating an internal clock signal by inputting the external clock signal in a semiconductor memory device includes: a first frequency dividing means for dividing a frequency of a clock signal having the same cycle as the external clock signal to generate a first clock signal; a second frequency dividing means for dividing a frequency of the first clock signal to generate second and third clock signals of different pulse widths; a select signal generating means for generating a select signal corresponding to a frequency of the external clock according to a plurality of control signals; and a clock signal selecting means for selectively outputting the second clock signal or the third clock signal in accordance with the select signal.


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Inventors:
JEON YOUNG-JIN
Application Number:
JP2003160437A
Publication Date:
February 12, 2004
Filing Date:
June 05, 2003
Export Citation:
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Assignee:
HYNIX SEMICONDUCTOR INC
International Classes:
G06F1/06; G11C8/00; G11C11/407; H03K21/00; H03K21/10; H03K23/66; H03L7/081; (IPC1-7): H03K21/00; G06F1/06; G11C11/407; H03K23/66; H03L7/081
Domestic Patent References:
JPH04172716A1992-06-19
JPH05268072A1993-10-15
JP2000148255A2000-05-26
JPH01261915A1989-10-18
JPH06350438A1994-12-22
Attorney, Agent or Firm:
Teruichi Hase
Maki Kamiya