To provide a clock frequency divider and a clock frequency dividing method in a delay locked loop in which a frequency of an inputted external clock is automatically divided into a low frequency band or a high frequency band and an optimal divided frequency waveform is selected in accordance with the band.
The clock frequency divider in a DLL circuit for generating an internal clock signal by inputting the external clock signal in a semiconductor memory device includes: a first frequency dividing means for dividing a frequency of a clock signal having the same cycle as the external clock signal to generate a first clock signal; a second frequency dividing means for dividing a frequency of the first clock signal to generate second and third clock signals of different pulse widths; a select signal generating means for generating a select signal corresponding to a frequency of the external clock according to a plurality of control signals; and a clock signal selecting means for selectively outputting the second clock signal or the third clock signal in accordance with the select signal.
JPS59192742 | [Title of the device] Data-processing circuit |
JPH06111035 | MICROCOMPUTER |
JPH04172716A | 1992-06-19 | |||
JPH05268072A | 1993-10-15 | |||
JP2000148255A | 2000-05-26 | |||
JPH01261915A | 1989-10-18 | |||
JPH06350438A | 1994-12-22 |
Maki Kamiya