Title:
クロック分周回路
Document Type and Number:
Japanese Patent JP4588786
Kind Code:
B2
Abstract:
A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.
Inventors:
Yamaguchi Hisakatsu
Koichi Kanda
Junji Ogawa
Yasutaka Tamura
Koichi Kanda
Junji Ogawa
Yasutaka Tamura
Application Number:
JP2008502575A
Publication Date:
December 01, 2010
Filing Date:
February 28, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K23/00; H03K5/00; H03K5/15
Domestic Patent References:
| JPH05347554A | 1993-12-27 |
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori
Toshihide Mori