To provide a clock frequency-dividing circuit which is capable of high-speed and stable switching and reducible in circuit scale.

In synchronism with timing of variation of a frequency-division clock signal to a low level, the clock frequency dividing circuit sets (n)-bit frequency division ratio data corresponding to a frequency division ratio for a basic clock signal of the frequency-division clock signal and also sets (n)-bit 1/2 frequency-division ratio setting data obtained by halving the frequency-division clock ratio setting data. When count data from a counter match the 1/2 frequency-division ratio setting data, a frequency-division clock set signal for varying the frequency-division clock signal to a high level is generated. When the count data from the counter match the frequency-division ratio setting data, a frequency-division clock reset signal for varying the frequency-division clock signal to the low level is generated. The frequency-division clock signal is varied to the high level in accordance with the frequency clock set signal and varied to the low level in accordance with the frequency-division reset signal.