To frequency-divide an input clock by n/m ((n) and (m) are set to be arbitrary natural numbers and it is set to be n<m) by providing an m-ary addition means adding the output of a latch means with the output of a setting means and outputting an added result and outputting the carry value of the m-ary addition means as an output clock.

The clock n/m frequency-dividing circuit 10 is provided with the m-ary addition circuit 11, a first register (1) 12 and a second register (2) 13. In the register 12, a setting value (n) is set by a setting signal and it is inputted to one input side of the m-ary adder 11. In the register 13, the output of the m-ary addition circuit 11 is latched by the input clock and the latched output of the register 13 is fed back to the other input side of the m-ary addition circuit 11. The m-ary addition circuit 11 adds the output of the register 12 and the output of the register 13, and the added value is outputted as the output clock at the time of carrying.