Title:
CLOCK-GENERATING CIRCUIT, INFORMATION REPRODUCING DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR THE DESIGNING CLOCK-GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2007300450
Kind Code:
A
Abstract:
To provide a clock-generating circuit for generating a plurality of clocks at low cost by saving power consumption without having to use a PLL, and to provide an information-reproducing device, and an electronic apparatus, etc.
The clock-generating circuit 200 generates a first output clock and a second output clock having a frequency f0, based on an input clock iclk having a frequency fH. The circuit 200 includes a first frequency division counter for generating the first output clock, obtained by dividing the frequency of the input clock or the clock, after thinning the input clock by a first frequency division ratio d1 (d1 is a positive integer); a second frequency division counter for generating the second output clock, obtained by dividing the frequency of the first output clock by the second frequency division ratio d2 (d2 is a positive integer); and a thinning control part for controlling the thinning of the input clock that is to be divided in frequency by the first frequency division counter, based on the second output clock.
COPYRIGHT: (C)2008,JPO&INPIT
Inventors:
KIMURA TSUNENORI
Application Number:
JP2006127269A
Publication Date:
November 15, 2007
Filing Date:
May 01, 2006
Assignee:
SEIKO EPSON CORP
International Classes:
H03L7/00; G06F1/06; H03K23/66
Attorney, Agent or Firm:
Inoue Ichi
Takekoshi Noboru
Enami Tomokazu
Yasushi Kuroda
