To enable generation of clock signal of a desired frequency from one reference signal in a clock generating circuit for generating a clock signal multiplied or divided in frequency from the reference signal.

The clock generating circuit 1 includes a pulse delay circuit 10 formed of m delay elements DU linked like a ring, a period measuring unit 20 for generating period data DT indicating a period of the reference signal CKI in unit of the delay time in the delay element DU based on the passing signals P1 to Pm sequentially output from each delay unit DU, a setting value register 50 for storing a setting value MN used as a divisor or a multiplier, a control unit 30 for generating control data CD indicating an output period of a clock signal by multiplying or dividing the setting value MN in the period data DT, and an output unit 40 for outputting the clock signal CKO obtained by dividing or multiplying the reference signal CKI based on the control data CD and passing signals P1 to Pm. The clock generating circuit 1 uses the setting value MN indicated by a real number.