CLOCK GENERATING CIRCUIT OF SWITCHED CAPACITOR CIRCUIT

Title:

CLOCK GENERATING CIRCUIT OF SWITCHED CAPACITOR CIRCUIT

Document Type and Number:

Japanese Patent JPS6074815

Kind Code:

A

Abstract:

PURPOSE: To form a delay circuit in a small circuit scale by replacing a delay circuit using a train of inverters with a delay circuit using a capacitor.

CONSTITUTION: A clock signal 0 having a 50:50 time ratio between L and H levels is supplied to an input terminal. The signal 0 is led to the input at one side of an NOR circuit 111 as well as to the input at one side of an NOR circuit 112 via an inverter circuit 121. The output of the circuit 111 is led to the input at the other side of the circuit 112 via a delay circuit 221 consisting of an inverter circuit 122 and a capacitor 211 as well as to output terminals 171 and 172 via an inverter circuit 124. Then clocks 1 and 2' are delivered from terminals 171 and 172. While the output of the circuit 112 is led to output terminals 181 and 182 via an inverter circuit. The clocks 2 and 2' are delivered from terminals 181 and 182. In such a constitution of a delay circuit using a capacitor, a large delay time is obtained with a small area.

Inventors:

NAKAYAMA KENJI
URIYA HIROSHI
HABUKA RIYUUJI
KIMURA TADAKATSU

Application Number:

JP18259883A

Publication Date:

April 27, 1985

Filing Date:

September 30, 1983

Export Citation:

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