To provide a clock generating circuit in which an output clock of a weak side band can be obtained by relaxing periodicity even on such an output frequency generation condition that periodicity may occur.

A counter 22 counts the number of reference clocks CLKref and applies a count value CNT to a comparator circuit 24. An adder 26 adds a Q output of a DFF 28 of N+M bits to a frequency setting value from an input terminal 14 and applies an addition result to a D input of the DFF 28. The DFF 28 latches the output of the adder 26 in accordance with rising and falling of an enable signal EN from the comparator circuit 24 and the reference clock CLKref. An adder 32 adds a random value from a random value generating circuit 30 to high-order N bits in the Q output from the DFF 28 and applies an addition result to the comparator circuit 24. The comparator circuit 24 outputs the enable signal if both the inputs are equal. A DFF 18 of which the Q output is fed back and connected to the D input by an inverter 20, shifts the Q output from high to low or inversely in accordance with the enable signal and the reference clock CLKref.