PURPOSE: To send/receive an accurate timing of data processed with a clock whose frequency division ratio is different by resetting a frequency divider circuit to take synchronization so that an ANDing clock of frequency divider clocks of a frequency divider circuit and a frame clock whose period is a least common multiple of the period of the frequency division clock are coincident with each other for their leading edge positions.

CONSTITUTION: A source clock CLK is sent to a frame generating circuit 1 to generate a frame clock with a period being a least common multiple between a 1st frequency division ratio by a 1st frequency divider circuit 3 and a 2nd frequency division ratio by a 2nd frequency divider circuit 4 and the clock is given to a set terminal S of flip-flops FF 5, 6. The clock CLK is inverted by an inverter 2 and given to a clock terminal C of the FF 5, 6. The circuits 3, 4 receive the clock CLK to generate 1st and 2nd frequency division clocks and 1st and 2nd control clocks being ANDing clocks of them are outputted and given to a data input terminal D of the FF5, 6, and an output terminal 9 of the FF5, 6 is used to output a reset signal of the circuits 3, 4. Thus, an accurate timing is obtained.