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Title:
CLOCK GENERATING METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2015188127
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a clock generating method and a semiconductor device that can reduce deviation from a target frequency and time fluctuation and reduce the consumption power and the cost.SOLUTION: In a clock generating method for generating clocks of a target frequency by dividing the frequency of an input clock, the frequency of the input clock is divided by the target frequency and a predetermined integer number k (k≥2) to determine a quotient and calculate a first divisional frequency value. A second divisional frequency value is calculated based on the first divisional frequency value, the frequency of the input clock is divided on the basis of the second divisional frequency value in one section out of k sections into which the time of one period of the target frequency is divided, and the frequency of the input clock is divided on the basis of the first divisional frequency value in the residual sections of k-1, thereby outputting clocks having the frequency at which the time corresponding to the sections of k into which the frequency of the input clock is divided is set as one period.

Inventors:
HABUKA TAKAMITSU
Application Number:
JP2014064338A
Publication Date:
October 29, 2015
Filing Date:
March 26, 2014
Export Citation:
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Assignee:
LAPIS SEMICONDUCTOR CO LTD
International Classes:
H03K21/02; G06F1/08; H03K23/64
Domestic Patent References:
JPH09232952A1997-09-05
JPH1198007A1999-04-09
JP2003101599A2003-04-04
JP2002043929A2002-02-08
JPH1155108A1999-02-26
JPH05284010A1993-10-29
JP2010087820A2010-04-15
JP2013034174A2013-02-14
Attorney, Agent or Firm:
中島 淳
加藤 和詳
福田 浩志