To provide a clock generation circuit which can switch an input clock and switch a division ratio accompanying it in a state of operating a PLL without causing out-of-synchronization.

A timing control part 8 switches a clock selection command SELCK according to an output of a reference clock CLKREF by a frequency divider 1 after clock selection information which specifies an input clock is switched and switches a setting of at least one of a number R of the input clock which makes the frequency divider 1 output one reference clock CLKREF and a number F of an output clock CLKO which makes a frequency divider 6 output one feedback clock CLKFB. The timing control part 8 starts both a count operation by the frequency divider 1 of the input clock corresponding to the switched setting number R and a count operation by the frequency divider 6 of the output clock corresponding to the switched setting number F.