Title:
CLOCK GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JP2014135550
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To generate a clock signal of 256 fs having a constant time interval from a signal rise to the next signal rise from a clock signal of 192 fs.SOLUTION: An input clock signal CK1 with a constant duty ratio is doubled in frequency to generate a clock signal CK2. From the clock signal CK2, a clock signal CK4 with a duty ratio of 2/3 having "H" over two clocks of the clock signal CK2 and next "L" over one clock is generated. The clock signal CK4 is delayed by one and a half clocks of the clock signal CK2 to generate a clock signal CK6. An inverted signal of the clock signal CK6 and the clock signal CK4 are subjected to an exclusive OR operation to generate a clock signal CK8.
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Inventors:
TAKAGI YOSHIKAZU
IGARASHI KAZUMASA
IGARASHI KAZUMASA
Application Number:
JP2013001117A
Publication Date:
July 24, 2014
Filing Date:
January 08, 2013
Export Citation:
Assignee:
NEW JAPAN RADIO CO LTD
International Classes:
H03K5/00; H03K23/64
Domestic Patent References:
| JPH11163689A | 1999-06-18 | |||
| JPS62227220A | 1987-10-06 | |||
| JP2002344308A | 2002-11-29 | |||
| JPS61230427A | 1986-10-14 | |||
| JPS6379420A | 1988-04-09 | |||
| JPH11355107A | 1999-12-24 | |||
| JPH0559975U | 1993-08-06 |
Attorney, Agent or Firm:
Tsuneaki Nagao