Title:
CLOCK GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JP3181471
Kind Code:
B2
Abstract:
PURPOSE: To make it possible to excellently generate a clock signal for reproduction in a DPLL at the time of pulling in a clock signal and after it by correcting the detection timing by a detection axis cross detection means and imparting the timing to the DPLL.
CONSTITUTION: Each of detection axis cross detection means 701 and 703 detects the timing in which each inputted phase difference signal 5 crosses the detection axis of the prescribed value set to its own signal and notifies the detection timing to a locus classification means 710. The means 710 discriminates and classifies the changed locus of the phase difference signal based on the detection timing by each detection axis cross detection means and outputs the timing adjustment signal according to the classification result to a timing control means 707. The means 707 corrects the detection timing by any detection axis cross detection means that the timing adjustment signal instructs for only the time that the timing adjustment signal instructs and imparts the timing as the phase signal for clock reproduction to a DPLL 72.
Inventors:
Seizo Nakamura
Application Number:
JP13552894A
Publication Date:
July 03, 2001
Filing Date:
June 17, 1994
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H04L27/22; H03L7/08; H04L7/00; H04L7/033; H04L27/227; (IPC1-7): H04L27/22; H04L7/00; H04L27/227
Domestic Patent References:
| JP5236043A | ||||
| JP6152667A | ||||
| JP646095A | ||||
| JP61114612A | ||||
| JP4229750U |
Attorney, Agent or Firm:
Kenji Ohnishi
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