PURPOSE: To widely hold a clock pulse width while guaranteeing the minimum value of a slit width by suppressing the fluctuation of the clock pulse width and the slit width of a clock with two phases in a digital circuit.

CONSTITUTION: An FF circuit 4 incorporating two delay circuits composed of the multiple-stage connection of gates, a detection circuit 2 detecting the output pulse of the circuit 4, a pulse generation circuit 1 generating a pulse from the timing of a delay circuit 3 and an OR gate circuit 5 are provided. The constitution of a circuit block (b) is the same as that of a circuit block (a) and a clock 2 is clock-generated 1 as against a clock 1. Then, the pulse widths T1M and T2M of the output signals 1M and 2M are respectively shown by expressions I and II. Thus, the relation between transmission delay time Td and the pulse width T1M and T2M is obtained and the fluctuation of the clock pulse width and the slit width can be suppressed to 1/2, for example, while the minimum value of the slit width of the clock signal is generated.