To provide a DLL circuit that generates a high precision clock in a small circuit scale and simple design configuration.
The DLL circuit includes: a clock generation section 100 for generating, from an externally input operating clock clks, an input clock having a different or same frequency from or as the operating clock and a set value k indicating a desired frequency, a generated clock clkc having a frequency that is the operating clock frequency divided by the set value k; a phase comparison section 200 for comparing the generated clock clkc with an externally input reference clock clkr in phase and outputting a phase difference; and a correction section 300 for generating a correction value for correcting the set value k to bring the phase difference to "0" in accordance with the phase difference output from the phase comparison section 200, and adding the correction value to the set value k.
| JPH0787357 | [Title of Invention] Divider Circuit |
MIYANOHANA KOSHI
MINEGISHI TAKAYUKI
| JP2007228043A | 2007-09-06 | |||
| JP2010200090A | 2010-09-09 | |||
| JP2000124779A | 2000-04-28 | |||
| JP2001298362A | 2001-10-26 |
Hiroto Yamachi
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