Title:
小数位相検出器を用いたクロック生成
Document Type and Number:
Japanese Patent JP5044719
Kind Code:
B2
Abstract:
Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.
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Inventors:
Noveli, Paolo
Cucci, silbio
Guastini, Giovanni
Cucci, silbio
Guastini, Giovanni
Application Number:
JP2011509463A
Publication Date:
October 10, 2012
Filing Date:
December 15, 2008
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H03K5/26; G06F1/04; H03K23/66; H03L7/06
Domestic Patent References:
| JP2005521322A | ||||
| JP200276886A |
Foreign References:
| US5907253 | ||||
| US6809598 |
Attorney, Agent or Firm:
Fukami patent office