PURPOSE: To generate mutually opposite-phase clock signals almost without delay by specifying the amount of delay of a signal at inverters.

CONSTITUTION: Inverters 4, 8, and 9 are so formed that the delay amount of the signal at the inverter 4 which generates a clock signal out of phase with a clock signal 1 is equal to those of inverters 8 and 9 which generate the clock signals 1. Further, inverters 7, 10, and 11 are so formed that the delay amount of the signal of the inverter 7 which generates a clock signal out of phase with a clock signal 2 is equal to those of the inverters 10 and 11 which generate the clock signal 2. Consequently, mutually oppsite-phase clock signals are generated almost without delay.