To provide a method for reducing the power consumption of a digital circuit while maintaining an operation with a high frequency.

This is a clock mechanism which uses an outside clock signal with a frequency F, and generates an inside master clock signal with lower frequency (for example, 1/2) than the frequency F. The inside master clock signal acting at a speed which is 1/2 of the speed of the outside clock is route- designated to a device (for example, the input of output buffer of a synchronizing memory product), which needs the clock signal across the whole device. The flow of a narrow pulse corresponding to the rising edge and falling edge of the inside master clock signal is locally generated to a part, which needs the clock signal of all frequencies. The flow of this narrow pulse has the frequency F.