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Patent Searching and Data


Title:
CLOCK MULTIPLICATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH10215153
Kind Code:
A
Abstract:

To generate a highly precise clock waveform by generating a pulse waveform by using either a rise waveform or the fall waveform in two clock signals outputted from a delay line circuit.

Signals D1-D3 with an equal delay time difference are taken out from an external clock inputted to the delay line circuit 10. The external clock and the signal D1 are inputted to an R S flip flop 21 and the pulse waveform E1 whose period is set to be an 'L' level is generated with the difference of delay time from the rise of the external clock to the rise of the signal D1. The signals D2 and D3 are inputted to an R S flip flop 22 and a pulse waveform E2 is similarly generated. The signals of the pulses E1 and E2 are synthesized in a HAND circuit 30 and a two-fold clock is obtained. Since the waveforms E1 and E2 in the part of the difference of delay time are generated by using only the rise of the waveforms of the external clock signal and the signals D1-D3, the difference does not occur in the pulse width of the waveforms E1 and E2.


Inventors:
HIRANO KATSUSHI
Application Number:
JP1692197A
Publication Date:
August 11, 1998
Filing Date:
January 30, 1997
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K5/00; (IPC1-7): H03K5/00
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)