To provide a clock multiplying circuit which can make a frequency comparison fast, has a short lock-in time, is stable and has less jitter for generating a clock signal of high frequency with a large multiplication number from an input clock signal of low frequency.

This clock multiplying circuit is equipped with a counter 11 which counts pulses of a specific output clock signal, an expected value generating circuit 10 which generates an expected value as to the number of pulses of the specific output clock signal per 1st clock much longer than a cycle of the specific output clocks signal, a comparing circuit 12 which compares the count value of the counter with the expected value in every 1st cycle and outputs comparison information regarding the comparison result, a delay control circuit 13 which generates a delay control signal indicating variation in the frequency of the specific output clock signal according to the comparison information, and an output clock signal generating circuit which generates the specific output clock signal while varying the frequency according to the delay control signal.