To obtain a clock non-hit switching device that can realize a non-hit switching, only by providing a circuit simpler than a PLL in each slave unit.

A clock synchronization unit 100a and a clock synchronization unit 100b output clock CLK2, CLK4 that are highly phase-locked to a slave unit 200. A selector 12C selects a clock fed to a function section 16 which is under the control of a switching control section 15. The switching control section 15 controls the selector 12C, so that switching is conducted for a period when the clocks CLD2, CLK4 are both at L or H level.