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Patent Searching and Data


Title:
CLOCK OBSERVING CIRCUIT
Document Type and Number:
Japanese Patent JPH04340486
Kind Code:
A
Abstract:

PURPOSE: To make small an operation clock cycle of an entire circuit device by a method wherein clock skew at an external terminal for clock observation of each printed wiring board is reduced to the minimum, in the circuit device constructed of a number of printed wiring boards.

CONSTITUTION: In each wiring board 1, clock supply lines 4a to 4e from IC 3 for clock supply to ICs 2a to 2e and clock supply lines 5a to 5e from the ICs 2a to 2e to observation terminals 6a to 6e corresponding to the ICs respectively are made equal in length respectively. A relay terminal 7 for relaying a clock for observation to an external terminal 9 and one of the observation terminals 6a to 6e are connected with each other by a wiring 10. When one of the observation terminals which has a phase being nearest to the midpoint of the maximum of a clock phase shift at each observation terminal is selected and connected to the relay terminal, clock skew of each wiring board becomes minimum and a clock cycle of an entire circuit device can be made small.


Inventors:
OMAE KENICHI
ISHIZUKI HITOSHI
Application Number:
JP14112491A
Publication Date:
November 26, 1992
Filing Date:
May 16, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F1/10; H03K5/13; G01R31/28; (IPC1-7): G01R31/28; H03K5/13
Attorney, Agent or Firm:
▲柳▼川 信