Title:
クロック分周回路
Document Type and Number:
Japanese Patent JP5609326
Kind Code:
B2
Abstract:
A clock divider circuit has a plurality of dividers for which dividing ratios are settable, a preset register group that stores the dividing ratios set for the plurality of dividers, and a selector that selects a single preset register within the preset register group, and imparts the dividing ratios stored in the selected preset register to the plurality of dividers.
Inventors:
久米 隆之
Application Number:
JP2010150929A
Publication Date:
October 22, 2014
Filing Date:
July 01, 2010
Export Citation:
Assignee:
富士通セミコンダクター株式会社
International Classes:
G06F1/08; H03K21/00
Attorney, Agent or Firm:
Furuya History Wang
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