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Title:
CLOCK PHASE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH0879323
Kind Code:
A
Abstract:

PURPOSE: To obtain a clock phase detection circuit in which a clock phase at a sampling time is detected from a digital modulation signal having only a specific frequency component.

CONSTITUTION: A chirp conversion circuit 2 applies chirp-Fourier conversion to a received digital modulation signal, them, the result is outputted to a synthesis circuit 5 via an orthogonal detector 3 and A/D converters 4a, 4b. The synthesis circuit 5 outputs a Fourier transformation signal for one symbol block to a sampling circuit 7 as a Fourier transform signal for plural symbol periods. The sampling circuit 7 applies sampling to the signal in a timing corresponding to a specific two-frequency component and a transformation table 9a detects the phase of the specific two-frequency component and a difference circuit 10 obtains the phase difference of each of phases and the result is outputted to the transformation table 9b. A transformation table 9b outputs a clock phase depending on the phase difference outputted from the difference circuit 10 to a filter 11, which smooths a clock phase signal and outputs a result.


Inventors:
KUMAGAI TOMOAKI
KOBAYASHI SEI
KATO SHUZO
Application Number:
JP20767094A
Publication Date:
March 22, 1996
Filing Date:
August 31, 1994
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G01R25/00; H04L7/00; H04L27/22; (IPC1-7): H04L27/22; G01R25/00; H04L7/00
Attorney, Agent or Firm:
Masatake Shiga



 
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