To provide the clock phase synchronization circuit by which phases of clock signals generated through frequency division at a clock control section such as a data transmission terminal station equipment of a dual system or the like are always synchronously with each other.

Clock pulses CP0, CP1 with 64 kHz of 0 and 1 systems are frequency-divided into 1/512 by synchronization counters 120, 121 and clock signals CK0, CK1 with 125 kHz are outputted from respective output terminals Q9. On the other hand, counts CNT0, CNT1 of the synchronization counters 120, 121 are given respectively to ANDs 130, 131 and synchronizing signals SYN0, SYN1 are outputted when the value of the ANDs 130, 131 reach 511. The synchronizing signals SYN0, SYN1 are given to selectors 140, 141 and the synchronization counters 120, 121 are reset by the synchronizing signals SYN0, SYN1 selected by a selection signal SEL.