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Title:
CLOCK RATE CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5428535
Kind Code:
A
Abstract:

PURPOSE: To increase the overall process velocity for the bus-type information transfer processor, by changing the duration of the synchronous clock in accordance with the device when the low-speed or high-speed device receives an access.


Inventors:
TAKECHI HIROAKI
YAMAZAKI MASASHI
ISOBE HITOSHI
Application Number:
JP9376777A
Publication Date:
March 03, 1979
Filing Date:
August 05, 1977
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/42; G06F1/08; G06F1/12; G06F5/06; (IPC1-7): G06F5/06
Domestic Patent References:
JPS5133380A1976-03-22
JPS5086940A1975-07-12
JPS5176036A1976-07-01
JPS52150941U1977-11-16



 
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