Title:
CLOCK RECOVERY CIRCUIT FOR DEMODULATOR
Document Type and Number:
Japanese Patent JP3230018
Kind Code:
B2
Abstract:
PURPOSE: To attain elimination of offset and high speed locking even when deviation is in existence in a carrier frequency by differentiating an output signal of a delay detector and extracting a conversion point so as to recover a clock signal.
CONSTITUTION: A phase detector 1 applies phase detection to an IF input signal in a QPS modulation wave and output modulation wave signal is given to a delay detector 2, from which output data are generated. The data are given to an offset circuit 41, in which the data are subject to +45° offset processing. This is an offset based on a carrier frequency deviation. Then the output is selected via a differentiation circuit 48 for a preamble signal at a selector 49 depending on a control signal and selected directly by the selector 49 for a unique word or data. The circuit 48 eliminates an offset in the output signal from the circuit 41. Then a conversion point extract section 42 detects an edge of the signal from which the offset is eliminated to extract the conversion point. Furthermore, A PLL 43 recovers the clock signal in following to the input and generates a recovered clock output.
Inventors:
Hideto Furukawa
Koji Matsuyama
Tomoki Sato
Koji Matsuyama
Tomoki Sato
Application Number:
JP1445693A
Publication Date:
November 19, 2001
Filing Date:
February 01, 1993
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L7/00; H04L7/033; H04L27/22; (IPC1-7): H04L27/22; H04L7/00; H04L7/033
Domestic Patent References:
| JP4180326A |
Other References:
１９９１年電子情報通信学会春季全国大会講演論文集 分冊２ ，島方幸広 大沢英男”ＰＳＫベースバンド遅延検波復調器の構成と特性” ｐ．２−３６０
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)