PURPOSE: To prevent the skip of a phase or a frequency of a clock output attended with a changeover into a standby clock input in the absence of an external clock input by adopting a constitution such that the operation of a standby clock generator is synchronized with an active clock output just before the changeover to the active generator.

CONSTITUTION: A selection command signal supplied from a fault detection control section 14 to an output side selector 13 is supplied also to input side selectors 15, 16. That is, when the output of an active PLL 11 is normal and it is selected by the output side selector 13, an external clock input at an input terminal IN is selected by the input side selector 15 to obtain a clock input to the active PLL 11. In this case, the clock output of the active PLL 11 is selected by the selector 16 to be a clock input to the standby PLL 12. As a result, if an external clock input is interrupted, even if the active PLL 11 is in the self-running state or close thereto, the clock output of the standby PLL 12 keeps the synchronizing state to the clock output of the active PLL 11.