PURPOSE: To obtain a stable recovery clock at an earlier period regardless of the C/N by allowing a switch to select the 1st gate signal until a digital signal of a frame period is detected and to select the 2nd gate signal after the digital signal of frame period is detected.

CONSTITUTION: Until a digital synchronizing signal of frame period is detected by a frame synchronizing detection section 24, a line synchronizing detection section 23 forms a gate signal (LGS) to extract the clock component is formed by a line synchronization detection section 23, it is applied to a clock recovery section 21 as a clock gate signal via a switch 25. After the digital signal of frame period is detected, a gate signal (FGS) formed by the frame synchronizing section 24 is fed to a clock recovery section 21 via the switch 25. Thus, the locking of clock recovery operation is quickened and the stable operation of the clock recovery operation is obtained after the detection of the frame period signal.