PURPOSE: To obtain a regenerated clock that follows input data by controlling the edge position of the regenerated clock in a regenerated clock generating means so as to be one-sidedly forwarded or delayed to the edge of the input data.

CONSTITUTION: In a FALSE-LOCK preventing circuit 41, flip flops(FF) F1-F4 are initialized at the time of rising of a RCLK. An output Q3 of the FFF3 is 1, an output Q4 of the FFF4 is 0, and a normal pull-in state is obtained. When the outputs Q3/Q4 are 1/0 or 0/1 at the time of rising of a CLK2, an output FLOCKN of an EX-OR3 is left 1, then the forced pull-in state is not obtained. When the outputs Q3/Q4 are 1/1 or 0/0 at the time of rising of the CLK2, the FLOCKN is 0, then the forced pull-in state is obtained. A FAST/ SLOW control circuit 21 continues the forced pull-in until the Q3/Q4 are 1/0 or 0/1 at the time of rising of the next RCLK based on the value of an SL2 and an FA12 from the circuit 41.