PURPOSE: To provide the clock selection circuit in which generation of a spike to an output waveform and disturbance of a width of a clock pulse are effectively prevented at the changeover of a clock signal.

CONSTITUTION: The clock selection circuit is provided with 1st and 2nd pulse generating circuits 13-16 generating a pulse synchronously with a trailing of 1st and 2nd clock signals respectively, a 2-input AND circuit 17 receiving an output of the 1st and 2nd pulse generating circuits, a latch circuit 18 using the output of the 2-input AND circuit 17 as a control input, using a clock selection signal as a data input and outputting the data input when the control input is at a high level and latching and outputting the data input hen the control input is at a low level, and selection circuits 11, 12, 19, 20 selecting the 1st and 2nd clock signals based on the output of the latch circuit.