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Title:
CLOCK SELECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS623350
Kind Code:
A
Abstract:

PURPOSE: To perform a clock switching action with no overlap nor omission by producing a selection signal synchronizing with own clock after confirming the non-selection of other clocks to own clock selection signal and selecting own clock.

CONSTITUTION: The clock signals CLK.AWC which are not synchronous with each other are switched by a selection output circuit 7 according to the selection signal applied to a decoder 8. When the signal CLK.A, for example, in selected, a selection signal SEL.A is selectable with signals SEL.B and C nonselectable respectively for the output of the decoder 8. A selection designating part 5-1 judges the outputs of synchronizing circuits 6-2 and 6-3 and confirms the non- selection of those outputs to send the selection signal SEL.A to a synchronizing circuit 6-1. This circuit 6-1 consists of shift registers A0WA2 which are shifted by a clock A. Thus the signal SEL.A for the clock A is synchronized with the clock A and applied to the circuit 7.


Inventors:
NOJIMA KENICHI
Application Number:
JP14230885A
Publication Date:
January 09, 1987
Filing Date:
June 28, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; G06F1/04; G06F1/08; (IPC1-7): G06F1/04; G06F11/22
Attorney, Agent or Firm:
Fumihiro Hasegawa



 
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