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Title:
CLOCK SIGNAL DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPS62180606
Kind Code:
A
Abstract:

PURPOSE: To allow the titled circuit to cope with a wide variety of input period and to attain the miniaturization by varying the time constant of the 1st monostable multivibrator and fixing the time constant of the 2nd monostable multivibrator.

CONSTITUTION: An inverted output B of a monostable multivibrator 10 changes from a value '1' to a value '0' at a point of time when an input clock A fed to a clock input terminal 50 changes from a value '0' to a value '1' and the state of value '0' continues for a time T1 only decided by a capacitance of a capacitor 13 and a resistance value between a slider terminal (a) of a variable resistor 12 and a terminal (b) not connected to a power supply. An output (c) of a monostable multivibrator 11 changes from a value '0' to a value '1' at a point of time T1 when the inverted output B changes from a value '0' to a value '1', and the state of value '1' continues for a time T2 only decided by a capacitance of a capacitor 15 and a resistance value of a resistor 14. The capacitance of the capacitors 13, 15 and the resistance value of the variable resistor 12 and the resistor 14 are selected so that the times T1, T2 satisfy equation (1), (2), where T is a period of the input clock A.


Inventors:
KUDO TOSHIYUKI
Application Number:
JP2251786A
Publication Date:
August 07, 1987
Filing Date:
February 04, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K5/13; (IPC1-7): H03K5/13
Attorney, Agent or Firm:
Naotaka Ide



 
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