To perform rational number frequency division of an input clock signal and phase adjustment of an output clock signal simultaneously without requiring a large circuit scale.

A delay indicated value calculating circuit 101 obtains a delay indicated value which is obtained by cumulatively adding M-N in every cycle of the input clock signal and generated by subtracting N from K when the delay indicated value K exceeds N, and increases or decreases the delay indicated value K according to a phase adjustment signal 30 showing phase control over the output clock signal. A control value output circuit 102 calculates a delay control value 104 corresponding to a delay amount of K/N of a unit delay amount per cycle of the input clock signal based upon the delay indicated value K. A variable delay circuit 200 imparts a predetermined delay amount to the input clock signal based upon the delay control value 104 to generate and output the output clock signal.