To suppress cycle time variation of an output clock signal frequency-divided by a rational number without requiring a large circuit scale, and to adjust the phase of the output clock signal during frequency division.

A clock selection control circuit 100 calculates a phase calculated value 111 showing phase relation between a reference frequency-division clock signal having a constant cycle time corresponding to a frequency division ratio and an input clock signal in every cycle of an input clock signal, and increases or decreases the value according to a phase adjustment signal 111 to generate control signals 102 and 103 indicating an output operation for generating a clock signal whose phase is close to that of the reference frequency-division clock signal among output operations based upon the phase calculated value 111. A clock selecting circuit 101 selects and executes one of output operations for outputting clock pulses of the input clock signal as they are without inverting them, for inverting and outputting the clock pulses, and for masking and not outputting the clock pulses based upon the control signals 102 and 103, thereby outputting the output clock signal.