To provide a rational frequency division circuit that reduces variations in the cycle time of a frequency-divided clock signal, increases opportunities of increasing a minimum cycle time of the frequency-divided clock signal with division ratio, reduces power consumption and layout area, and reduces a design/verification cost.

A clock signal frequency division circuit that specifies a division ratio as a ratio N/M of two integers N and M includes: a clock selection circuit for selecting whether to output an input clock signal as it is, output an inversion of the input clock signal or skip outputting the input clock signal; and control means for generating a control signal for controlling the selection of the clock selection circuit. The control means sets the division ratio at N/M, and the control means controls the selection of the clock selection circuit so as to approximate the phase of an ideal frequency-divided clock signal having a constant cycle time at every cycle of the input clock signal.